A large community of developers has emerged over the past 5 years in support of open source for embedded applications. Towards this end, the linux operating system has been customized to run on a wide variety of the special-purpose microprocessors commonly used in embedded systems. This embedded version of linux is called uClinux ("you-see-linux"). One group within this community focuses on making uClinux compatible with the Analog Devices Blackfin series of DSPs. We are currently researching mixed FPGA / DSP embedded applications and found that using the Analog Devices EZ-FPGA daughterboard in conjunction with Analog Devices evaluation boards for the BF537 processor caused problems in uClinux. This article describes our approach for successfully using the two boards together. This requires hardware modifications on the EZ-FPGA board which we describe in detail in this article.

Hardware modifications to the FPGA daughter card were necessary to make the card work with the BF537 EZKit Board (or the BF537 STAMP board). The hardware modifications involve disconnecting those wires associated with the BF537 ethernet interface and several other connections, all of which are located on the 90-pin header J3 that is part of the "U" shaped connector on the bottom of the board, also referred to as the Expansion interface type B. When connecting FPGA board to BF537 DSP board through that interface, some of pins on J3 connector will interfere with pins on network chip of BF537 board. Disconnecting them should get ethernet on bf537 work properly.The following image indicated  pins needed to be disconnected (marked with red block):


An image taken from the schematics of the FPGA daughter card is included. Those connections which must be disabled to make the daughterboard operate are in red. We accomplished this by simply lifting off the corresponding feet of these connections on J3 expansion interface board which, if necessary, we may re-attach at a later time.

There are also some useful tips that one should be aware of when using the FPGA daughter card with these BF537 development boards. We use the Xilinx ISE 9.2i to write VerilogHDL code for the FPGA. There are some important default settings that must be changed to make sure the BF537 will still operate properly when connected to the FPGA daughterboard. Specifically, in Xilinx ISE under the process property window one must change the configuration option for unused I/O pins. The default setting for unused I/O pins is "PULL UP," this setting must be changed to "FLOATING."

As a final note, one must also properly configure the FPGA board jumpers to ensure both FPGA and BF537 can boot up and that the FPGA board program is loaded from the onboard flash on reset.